• Configurable direction (per I/O)
• Output options include TTL, CMOS, opto-isolated, relay and current
• Up to 98 GPIOs available
• I/Os can be polled, or interrupt driven
• Interrupts can be confiured for rising edge, falling edge or both

• 16 counter / trigger channels per core, total number of channels limited only by FPGA space.
• Each counter is 30 bits wide
• Automatic reload of counter value on roll-over
• Enables periodic interrupt based on event triggering
• Can be disabled by zeroing the reload value
• No loss of counted events because reload value is accumulated
• Enable/Disable of rollover interrupt
• Counters can be (re)initialized at any time
• Includes support for quadrature encoder counting
  
  

Pulse Width Modulation

• Arbitrary pulse generator
• Up to 5 pulses with programmable delay, duty cycle (up to 64 K clock cycles)
• Capable of using timing clock source asynchronous to EMIF bus
• Capable of continuous operation using a 100 Mhz input clock
• Capable of fixed time operation up to 496 M clock intervals
• Capable of external or software derived triggering
• Minimum pulse widths / increments of 180 ns at 100 Mhz input clock
• Software notification via interrupt or semaphore

Other Digital Interfaces

I²C

• FPGA core implements data transfer protocol
• Software interface via FIFO
• Supports up to 8 devices
  

SPI