CPU
Texas Instruments TMS320C645x DSP

• Input clock 50MHz
• 700MHz internal clock rate (via internal PLL)
• Interface (EMIF) 100 MHz
• DDR2 SDRAM clocked at 250 MHz

Performance

Memory Architecture (Cache)

• 32K-Bit (4K-Byte) program cache (L1P)
• 32K-Bit (4K-Byte) data cache (L1D)
• 8192K-Bit (1024K-Byte) RAM / cache (L2)

I/O

• 32-bit wide EMIF FPGA/FLASH interface 
• 32-bit wide DDR SDRAM Controller
• 2 multichannel buffered serial ports (McBSPs)
• 1 I2C two wire interface

Interrupts

• 2 routed to FPGA

IEEE-1149.1 (JTAG)
Development Tools

• JTAG Emulation

FPGA
Xilinx Spartan-3 XC3S2000

Capacity

• 46,080 Logic cells
  - 99% available for application use

Performance

• Input clock 50/100 MHz
• Internal clock rate up to 300 MHz

I/O

• CPU processor bus, 14 address, 32 data, 3 CE, R/W, strobe, hold
• 140 configurable I/O pins (4 Banks)
  • Bank Voltage Configurable (3.3 or 2.5 V)
  • Single ended or LVDS capable
  • Routed to MityDSP-PRO DIMM connector

IEEE-1149.1 (JTAG)
Development Tools

• Xilinx ISE Tools

Memory Subsystem

Flash Memory 16M-byte

• Byte wide interface
• 90ns access time

DDR2 SDRAM 128M-byte

• 32-bit wide interface
• 4ns burst mode access time (250MHz)

DDR SDRAM 64M-byte FPGA Direct RAM

• 16-bit wide interface
• 10ns burst mode access time (100MHz)
  

Interface Connector

200 pin high density connector

• DDR2 DIMM type
• Mating connector part number
  •  
  •  

• I/O
  • 140 configurable I/Os (FPGA)
  • 2 McBSP channels (DSP)
  • JTAG (DSP, FPGA)
  • 1 12C
  • Ethernet
  • Serial Rapid I/O
  • Power, Ground

Actual Size 2.7” x 3”