MityDSP-XM Hardware

CPU
Texas Instruments TMS320C6711
floating point DSP

• Clock Rate
• Input clock 25MHz
• 200 MHz internal clock rate (via internal PLL)
• Interface (EMIF) 50 or 100 MHz

Performance

• 600 MFLOPS

Memory Architecture (Cache)

• 32K-Bit (4K-Byte) program cache (L1P)
• 32K-Bit (4K-Byte) data cache (L1D)
• 512K-Bit (64K-Byte) RAM / cache (L2)

I/O

• 32-bit wide interface
  Routed to SDRAM / FPGA / FLASH
  
• 2 multichannel buffered serial ports (McBSPs)
  Routed to MityDSP I/O connector

Interrupts

• 4 routed to FPGA

IEEE-1149.1 (JTAG)
Development Tools

• JTAG Emulation

FPGA
Xilinx Spartan-3 XC3S1000

Capacity

• 1000K logic cells
  - 90% available for application use

Performance

• Input clock 25 MHz
• Internal clock rate up to 300 MHz

I/O

• CPU processor bus, 12 address, 32 data, 4 CE, R/W, strobe, hold
  • General purpose I/O
  • 78 configurable I/O pins
    • 3.3V capable
    • Routed to MityDSP connector
  • 20 configurable I/O pins
    • 3.3V or LVDS capable
    • Routed to MityDSP connector

IEEE-1149.1 (JTAG)
Development Tools

• Xilinx ISE Tools

Memory Subsystem

Flash Memory 16M-byte

• Byte wide interface
• 90ns access time

SDRAM 32M-byte

• 32-bit wide interface
• 10ns burst mode access time (100 MHz)
  

Interface Connector

144 pin high density connector

• SO DIMM type
• Mating connector part number
  • 5-4189-1440 (Molex)
  • 390110-1 (AMP)

• I/O
  • 98 configurable I/Os (FPGA)
  • 2 McBSP channels (DSP)
  • JTAG (DSP, FPGA)
  • Power, Ground

Actual Size 2.7” x 1.5”