Comparison

The table below compares the MityDSP, MitydSP-XM, and the MityDSP-PRO CPU engines available for purchase today.  In addition, preliminary performance data is included for Critical Link's next generation MityDSP engine, the MityDSP-PROV30.  The PRO-V30 is anticipated for release in 2008.

Feature
MityDSP
MityDSP-XM
MityDSP-PRO
MityDSP-PROV30
TI DSP Processor
6711
6711
6454 / 555
6454 / 555
 Max CPU Speed [MHz]
200
200
7004
7004
 Integer MMACs
400
400
5760
5760
 Floating Point Whetstones
220
220
154
154
 Ethernet MAC / PHY
N/A3
N/A3
1
1
FPGA
XC3S400
XC3S1000
X3CS2000
XCV5L30T
 Slices
3,584
7,680
20,480
4,8002
 Logic Cells
8,064
17,280
46,080
30,720
 Block RAM
288 Kb
432 Kb
720 Kb
1,296 Kb
 Rocket I/O Xcvrs
0
0
0 / 8
0 / 8
 Ethernet 1Gbps MACs
03
03
03
4
Memory
 
 
 
 
 Cache / Internal RAM
64 K
64 K
2048 K
2048 K
 CPU RAM
8 M
32 M
128 M
128 M
 CPU RAM ThroughPut
400 MB/sec
400 MB/sec
2000 MB/sec
2000 MB/sec
 FLASH
2 M
16 M
16 M
16 M
 FPGA RAM
8 M1
32 M1
64 M
128 M
 FPGA RAM ThroughPut
400 MB/sec
400 MB/sec
400 MB/sec
400 MB/sec
Interface
SO-DIMM
SO-DIMM
DDR2 SO-DIMM
DDR2 SO-DIMM
 Required Voltages
3.3, 2.5, 1.23
3.3, 2.5, 1.23
3.3
3.3
 Available FPGA I/O
100
100
140
140
 No. Differential Pairs
10
10
70
70
 Max Data Rate (SSTL)
250 Mbps
250 Mbps
250 Mbps
TBS
 Max IData Rate (LVDS)
320 Mbps
320 Mbps
320 Mbps
TBS
 DSP McBSP Ports
2
2
2
2
 DSP I2C Ports
0
0
1
1
 FPGA JTAG
Yes
Yes
Yes
Yes
 DSP JTAG
Yes
Yes
Yes
Yes
Availability
In Production
In Production
In Production
3Q2008

 Notes:

  1. FPGA and CPU share 8 MBytes of RAM via DSP EMIF, 100 MHz clock rate maximum.
  2. The V5 uses 6 input lookup table (LUT) functions vs. 4 input LUTs on Spartans.
  3. Soft FPGA MAC cores are available for 10/100 Mbit Ethernet Phy Control.
  4. 1000 Mhz CPU configurations are available for MityDSP-Pro cards. 
  5. TMS6455 Option Including 8 Rocket I/O ports is available upon request.

 

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